Verilog Course Syllabus

1. General Description

1.1 Course Objectives

Studying Logic Design (with VERILOG), towards effective synthesis.

· Understand the structure of a VERILOG program.

· Implement a state machine and its associated test programs.

· Be-aware of hazards and risks by the migration of from High Level Design and synthesis.

1.2 Prerequisite

· At least one year of experience in high level language programming.

· Knowledge of digital design.

1.3 Course Organization

The course is composed of:

· The theory.

· Workshops in which the process of analyzing given designs and understanding their semantics, is performed.

· Practical exercising using Verilog tools.

This document describes:

· The lectures, workshops and the exercises to be given course.

· Hours allocation.

2. Course Subjects

2.1 Introduction to Verilog

2.1.1 Lecture

2.1.1.1 Overview

· Course objectives.

· Motivation for using Verilog.

· Verilog environment.

2.1.1.2 Top-Down Design Methodology

· Behavioral model.

· Structural model.

2.2 Hardware Modeling with Verilog

2.2.1 Lecture

· Declaration of Module Port

· Logical interface definition.

· Timing definition and checking.

· Module Implementation

2.2.2 Workshop

Presenting of Module Port of:

· One bit full adder.

· RS Flip-Flop (including timing checks).

2.2.3 Practical Exercising

2.2.3.1 Class

· Writing the Module Port of a RAM.

· Writing the Module Port of a sorting machine.

2.3 Structural and Behavioral Design

2.3.1 Lecture

· Structural Design

1. Explicit structural design.

1.1 Model Port connections: Binding by 1) name, 2) by position.

1.2 Primitive Terminal connections.

2. Implicit structural design.

3. Combinational logic implemented by Implicit and Explicit structural design.

· Behavioral Design

· RTL Data-Flow Description.

· Algorithm-Based description

2.3.2 Workshop

Presenting Structural models of:

· One bit full adder.

· RS Flip-Flop (including timing checks).

2.3.3 Practical Exercising

Give an Explicit Structural design.

· What is the function behind the Verilog description?

· Write the Implicit structural design.

· Write the RTL Dataflow Description.

· Sketch a test program for this description.

2.4 Objects in Verilog

2.4.1 Lecture

1. Signals.

1.1 Model of signal assignment statements:

· Transport delay – Net delay.

· Inertial delay –Gate propagation Delay.

1.2 Transaction of signals.

2. Variables.

2.1 Nets (wires): One directional, Bi-Directional.

2.2 Registers.

3. Synthesis semantics of Variables.

2.4.2 Workshop

· Transport and Inertial delay.

· Order of signal assignment.

· Simulation and Synthesis semantics of registers wires and signals.

2.4.3 Practical Exercising

2.4.3.1 Class

Write a test program for the RS flip-flop.

2.4.3.2 Homework

· Write the behavioral description of the same program.

· Write a test program for it.

· Run the two architectures concurrently.

2.5 Behavioral description

2.5.1 Lecture

· Overview of Sequential and Parallel statements.

· Sequential Statements:

· Assignment statements

· Conditional statements: ?, IF…ELSE, CASE.

· Loop statements: REPEAT, FOR, WHILE, FOREVER.

· DISABLE.

· Synthesis semantics of conditional and While/Loop statements.

· Parallel statements: FORK, JOIN.

· Race in FORK, JOIN statements.

· Task.

· Functions.

2.5.2 Workshop

1. Timing Checks

· Setup and Hold.

· Signal Period.

· Minimum Pulse Width.

2. Given several high level architectures which perform one of the following functions. Only two give the same results after being synthesized. Analyze these architectures and their performance (timing versus space).

Resolve a bit.

· Serial operation.

· Parallel operation.

· Finding the minimum of two numbers.

· Pipeline operation of finding the minimum of two numbers.

2.5.3 Practical Exercising

2.5.3.1 Class

Write a test program which runs concurrently high-level and low-level architectures.

2.5.3.2 Homework

Write and run a test program for Resolving a bit. Compare high level simulation results.

2.6 Various machine representations in Verilog

2.6.1 Lecture

Combinational networks.

Finite State Machines (FSM):

· Explicit FSM.

· Implicit FSM

2.6.2 Workshop

· Melay machine.

· Moore machine.

· FSM coding styles.

2.6.3 Practical exercising

2.6.3.1 Class

· Write the sorter machine as a state machine.

· Synthesize it.

· Write and run a test program for the high and low level architectures.

2.6.3.2 Homework

· Write a multiplier.

· Synthesis it.

· Write and run a test program for the high and low level architectures.

3. Hours Allocation

Course Subjects	Lecture	Workshop	Exercising in class	Total Hours
Introduction to Verilog	2			2
Hardware Modeling with Verilog	2	2	2	6
Structural and Behavioral Design	3	3	0	6
Objects in Verilog	2	6	0	8
Behavioral description	2	5	2	9
Various machine representations in Verilog	2	5	4	11
Total	13	21	8	42

4. Bibliography

[Chang97] K.C. Chang, Digital Design and Modeling with VERILOG and Synthesis,

IEE Computer Society Press, ISBN 0-816-7716-3.

[Navami] Zainalabedin Navami VERILOG Analysis and modeling of Digital Systems.

McGraw-Hill series in electrical and computer engineering, ISBN 0-07-046472-3.

[DoPer90] Douglas L. Perry, VERILOG second edition. McGraw-Hill series on

Computer Engineering, ISBN 0-07-049434-7, McGraw-Hill, 1990.

[LRM88] IEEE Standard VERILOG Language Reference Manual- std 1076-1987.

New York: IEEE 1988.

[Ams88] James. R Amstrong. Chip level Modeling with VERILOG. Englewood

Cliffs, NJ: Prentice Hall, 1988.

[Coh89] David Cohelho. A First course in VERILOG. Boston: Kluwer Academic,

1989.

[LipSc89] Roger Lipsett, Carl Schaefer, Cary Ussery VERILOG: Hardware

Description and Design. Boston: Kluwer Academic, 1989.

[Carison91] Steve Carison, Introduction to HDL-Based DESIGN Using VERILOG.

Synopsys Inc, 1991.