VHDL Course Syllabus

1. General Description

1.1 Course Objectives

· Studying Logic Design with VHDL towards effective synthesis.

· Understand the structure of a VHDL program.

· Implement a state machine and its associated test programs.

· Be-aware of hazards and risks by the migration of from High Level Design and synthesis.

1.2 Prerequisite

· At least one year of experience in high level language programming.

· Knowledge of digital design.

1.3 Course Organization

The course is composed of:

· The theory.

· Workshops in which the process of analyzing given designs and understanding their semantics, is performed.

· Practical exercising using VHDL tools.

This document describes:

· The lectures, workshops and the exercises to be given course.

· Hours allocation.

2. Subjects Covered in the course

2.1 Introduction to VHDL

2.1.1 Lecture

2.1.1.1 Overview

· Course objectives.

· Motivation for using VHDL.

· VHDL environment.

· Overview of CPLD, FPGA and ASIC.

2.1.2 Top-Down Design Methodology

Model types:

· Behavioral model.

· Structural model.

· Timing model.

2.2 VHDL Design Units and their relation

2.2.1 Lecture

2.2.1.1 Entity

· Logical interface definition.

· Timing definition and checking.

2.2.1.2 Architecture

· Behavioral model. A simple example of a basic gate will be given here.

· Structural model. High level design for structural models includes:

Component instantiation.

Component configuration

2.2.1.3 Component

· Physical interface definition.

· Timing definition.

2.2.1.4 Packages

· Package interface definition.

· Package body definition.

2.2.2 Workshop

Presenting Structural and Behavioral models of:

· One bit full adder.

· RS Flip-Flop (including timing checks).

2.2.3 Practical Exercising

2.2.3.1 Class

· Writing the ENTITY of a RAM.

· Writing the ENTITY of a sorting machine.

2.2.3.2 Homework

Given a structural VHDL design:

· What is the function behind the VHDL description?

· Sketch a test program for this VHDL description.

2.3 VHDL Objects

2.4 Lecture

1. Constants.

2. Signals.

3. Model of signal assignment statements:

· Transport delay.

· Inertial delay.

4. Transaction of signals.

5. Variables.

2.5 Workshop

· Transport and Inertial delay.

· Order of signal assignment.

· Simulation and Synthesis semantics of Variables and Signals.

2.6 Practical exercising (2 hour)

2.6.1 Class

Write a test program for the RS flip-flop.

2.6.2 Homework

· Write the behavioral description of the same program.

· Write a test program for it.

· Run the two architectures concurrently.

2.7 Behavioral description

2.7.1 Lecture

1. Overview of Sequential and Concurrent statements.

2. Sequential Statements:

· Assignment statements

· Conditional statements.

· While Loop statements.

3. Synthesis semantics of conditional and While/Loop statements.

4. Concurrent statements:

(a) Signal assignment statements:

i. Buffer model.

ii. Bi-Directional Bus description in VHDL.

(b) For-Loop statements.

2.7.2 Workshop

1. Given 4 high level architectures which find the minimum of two numbers. Only two give the same results after being synthesized.

Analyze these architectures and their performance (timing versus space).

2. Resolving a bit.

· Serial operation.

· Parallel operation.

2.7.3 Practical Exercising

2.7.3.1 Homework

Write and run a test program for Resolving a bit.

2.8 Behavioral description using Processes

2.8.1 Lecture

1. Definition.

2. Inter Process communication.

3. Process triggering and suspensions.

2.8.2 Workshop

Receiver-Transmitter.

2.9 Various machine representations in VHDL

2.9.1 Lecture

· Combinational networks.

· Finite State Machines (FSM).

2.9.2 Workshop

· Melay machine.

· Moore machine.

· FSM coding styles.

2.9.3 Practical exercising

2.9.3.1 Homework

· Write the sorter machine as a state machine.

· Write and run a test program.

2.10 Software Engineering with VHDL

2.10.1 Lecture

· Abstract data types.

· Subprograms.

· Managing shared libraries. Testing and verification.

2.10.2 Synthesis

· Semantics of VHDL constructs:

· Entity.

· Process.

· Package.

2.10.3 Clocks and timing models

· Process Independent Design.

· Implicit/Explicit Timing.

· Asynchronous operation.

3. Hours Allocation

Subject	Lecture	Workshop	Exercising in class	Total Hours
Subjects Covered in the course Introduction to VHDL	2			2
VHDL Design Units and their relation	2	1	2	5
VHDL Objects	3	7	0	10
Behavioral description	2	8	0	10
Behavioral description using Processes	2	2	1	5
Various machine representations in VHDL	2	6	0	8
Software Engineering with VHDL	2			2
Total	15	24	3	42

4. Bibliography

[Chang97] K.C. Chang, Digital Design and Modeling with VHDL and Synthesis,

IEE Computer Society Press, ISBN 0-816-7716-3.

[Navami] Zainalabedin Navami VHDL Analysis and modeling of Digital Systems.

McGraw-Hill series in electrical and computer engineering, ISBN 0-07-046472-3.

[DoPer90] Douglas L. Perry, VHDL second edition. McGraw-Hill series on

Computer Engineering, ISBN 0-07-049434-7, McGraw-Hill, 1990.

[LRM88] IEEE Standard VHDL Language Reference Manual- std 1076-1987.

New York: IEEE 1988.

[Ams88] James. R Amstrong. Chip level Modeling with VHDL. Englewood

Cliffs, NJ: Prentice Hall, 1988.

[Coh89] David Cohelho. A First course in VHDL. Boston: Kluwer Academic,

1989.

[LipSc89] Roger Lipsett, Carl Schaefer, Cary Ussery VHDL: Hardware

Description and Design. Boston: Kluwer Academic, 1989.

[Carison91] Steve Carison, Introduction to HDL-Based DESIGN Using VHDL.

Synopsys Inc, 1991.