Test &
Verification
The importance of the Test and Verification process in all the design stages is well known and well documented. However, it is also required that
1) the same test scenarios applied at the early stages of the design process, will be later injected to a real hardware component
2) the response of the real hardware component
under test will fit the theoretical response expected earlier.
The scenarios are algorithmically described
while the operation is a set of test vectors. Each set may have the size of
many thousands values for each pin of the component. Instead of manual production of the test vectors, we automatically generate
the test vectors as an output of a simulation run. The design is expressed in a
high-level hardware description language such as VHDL or Verilog.
The test may be written in HDL or using other algorithmic tools such as SpecMan of Verisity. The simulation of the design and the test produces
waveforms, which are input to a translator, which in turn generates the test vectors.
This technique may be applied to test adevice on a board after fabrication. The device is mounted on Automatic Test Equipment
(ATE), to detect:
The component is properly mounted with the direct orientation.
All the pins are neither shortened nor disconnected (no cold
soldering).
We have developed test programs running on the
GenRad228x family to test ISDN components. The developed test programs
include the following steps:
Simulate the stimulus in VHDL environment, while using special
constructs for
triggering and synchronization.
Derivation of the test vectors for the tester.
Injecting the test vectors to the component under test.
Comparing automatically the response of the component to the waveform
generated by the simulation to find miss-matches.
Integration of the test programs in the board.
The description of the development process of
a test program has been published in a paper of the 13’th
International Logistics Congress,
The list of test programs includes: ISDN
components, μ-processors, and DSP.