SystemC Course Syllabus

 

1.  General Description

1.1 Course Objectives

Studying Logic Design with SystemC towards effective synthesis.

1. Understand the structure of a SystemC program.

2. Implement a state machine and its associated test programs.

3. Be-aware of hazards and risks by the migration of from High Level Design and synthesis.

1.2 Prerequisite

1. At least 1 year of experience in high level language programming.
2. Knowledge of digital design.

1.3 Course Organization

The course is composed of:

1. Lectures in which the theory is given.
2. Workshops in which the process of analyzing given designs and understanding their semantics, is performed.
3. Practical exercising using SystemC tools.

 

This document describes:

1. The lectures, workshops and the exercises to be given course.
2. Hours allocation.

2. Subjects Covered in the course

2.1 Introduction to SystemC

2.1.1 Lecture

2.1.1.1 Overview 

1.      Course objectives.

2.      Motivation for using SystemC.

3.      SystemC environment.

4.      Overview of CPLD, FPGA and ASIC.

2.1.2 Top-Down Design Methodology 

Model types:

          ·          Behavioral model.

          ·          Structural/hierarchy model.

          ·          Timing model.

2.2 Module: Interface & Implementation 

2.2.1 Lecture

2.2.1.1 Module  Interface

1. Interface, Ports & Channels

2. Timing definition and checking.

2.2.1.2 Implementation

1. Behavioral model. A simple example of a basic gate will be given here.

2. Structural model. High level design for structural models includes instantiation of other modules:

• Module instantiation
• Port Binding: Name & position.

 

2.2.2 Workshop

Presenting Structural and Behavioral models of:

1. One bit full adder.

2. RS Flip-Flop (including timing checks).

2.2.3 Practical Exercising 

2.2.3.1 Class

1.  Writing the Module of a RAM.

2.  Writing the  Module of  a sorting machine.

2.2.3.2 Homework

 

1. Given a structural SystemC design.

1.1 What is the function behind the SystemC description?

1.2    Sketch a test program for this SystemC description.

2.3 SystemC Objects

2.3.1 Lecture

1.      Constants.

2.      Signals.

3.      Event: Event occurrence and notification.

4.      Variables.

2.3.2 Workshop

1.      Order of signal assignment.

2.      Simulation and Synthesis semantics of Variables and Signals.

2.3.3 Practical Exercising  (2 hour)

2.3.3.1 Class

1. Writing a test program for the RS flip-flop.

2.3.3.2 Homework

 

Consider again ‎2.2.3.2.

1.      Write the behavioral description of the same program.

2.      Write a test program for it.

3.      Run the two architectures concurrently.

2.4 Behavioral description 

2.4.1 Lecture

1.      Overview of Sequential and Concurrent statements.

2.      Sequential Statements:

·        Assignment statements

·        Conditional statements.

·        While Loop statements.

3.      Synthesis semantics of conditional and While/Loop statements.

4.      Concurrent statements:

(a)                Signal assignment statements:

i.                     Buffer model.

ii.                   Bi-Directional Bus description in SystemC.

(b)               For-Loop statements.

2.4.2 Workshop

1.      Given 4 high level architectures, which find the minimum of two numbers.  Only two give the same results after being synthesized. Analyzing these architectures and their performance (timing versus space).

2.      Resolving a bit.

·        Serial operation.

·        Parallel operation.

2.4.3 Practical Exercising

2.4.3.1 Homework

Write and run a test program for Resolving a bit.

2.5 Behavioral description using Processes 

2.5.1 Lecture

1.      Definition.

2.      Inter Process communication.

3.      Process triggering: Static and dynamic sensitivities

4.      Process suspensions.

 

2.5.2 Workshop

Receiver-Transmitter.

2.6 Various machine representations in SystemC

2.6.1 Lecture

1. Combinational networks.

2. Finite State Machines (FSM).

2.6.2 Workshop

1.      Melay machine.

2.      Moore machine.

3.      FSM coding styles.

2.6.3 Practical exercising

2.6.3.1 Homework

1.      Write the sorter machine as a state machine.

2.      Write and run a test program.

2.7 Software Engineering with SystemC 

2.7.1 Lecture

1.      Abstract data types.

2.      Managing shared libraries.

3.       Testing and verification.

2.7.2 Clocks and timing models

1.      Process Independent Design.

2.      Implicit/Explicit Timing.

3.      Asynchronous operation.

2.8 SystemC & HDL

1.      Instantiating System C in HDL

2.      Instantiating HDL in System C

3. Hours Allocation