System Design with VHDL Course Syllabus

 

1.  Course Objectives

After completing the course the student will:

 

1.   Giving a systematic approach to Hardware Development design steps: Requirement and Analysis, Design and Implementation.

2.   Configuration Management.

2. General Description

The course is composed of:

1.                        Lectures in which the theory is given.

2.                        Workshops in which the process of analyzing given designs and understanding their semantics, is performed.

3.                        Practical exercising using VHDL tools.

 

This document describes:

1.                        The subjects and the exercises to be given course.

2.                        Allocation of hours.

3. Course Subjects

3.1 HW Design flow

3.1.1 Lecture

1.                        History.

2.                        Motivation.

3.                        Life Cycle:

                            ·                Stages

                            ·                Deliverable items.

                            ·                Reviews

4.                        System Structure.

5.                        VHDL and its relation to software engineering issues.

 

3.1.2 Workshop

For a given design, we shall demonstrate:

1.                        The documents and data associated with that design.

2.                        Hierarchy of documents and data.

3.                        Sharing documents and data.

3.1.3 Practical Exercising

Creating a new project. Observing the documents and data associated with that project.

 

3.2 System Specification

3.2.1 Lecture

1.   What are the documents related to the system specification stages.

2.   Formal versus verbal documents.

3.   Formal system specification:

3.1 Data-Flow Diagrams (DFD):

                            ·                Data Structures.

                            ·                Control structures.

 

3.2 Final State Machine (FSM).

 3.3 Performance  issues:

                            ·                Thruput.

                            ·                Area

4.   Maintability and Build In Test.

5.   Testing the design.

3.2.2 Workshop

Given a problem definition in a verbal language, a system specification document will be derived by:

1.                        Formal definition using VHDL tools. Related issues:

1.1                   Information sharing.

1.2                   Abstraction.

1.3                   Information hiding.

2.                        Verbal documents using the formal definitions in (1) for:

                            ·                System Specification.

                            ·                Test plan document.

3.2.3 Practical Exercising

Perform the system specification stage.

3.3 Design

3.3.1 Lecture

 

1.   Architectural design: Functional decomposition to ENTITIEs and PROCESSes.

1.1 Resource usage.

1.2 Controlling the resources.

1.3 Reset: Synchronous and Asynchronous resets.

1.4 Clocking.

1.5 Performance  issues:

                            ·                Thruput.

                            ·                Area

2.   Using IP cores.

3.   Test Design

3.3.2 Workshop

Given a system specification document, the design documents will be derived by formal definition using VHDL tools. Related issues:

1.                        Top level architecture definition of ENTITIES.

2.                        For each ENTITY, either decompose it to ENTITIES or to PROCESSes

3.                        Private information inside an ARCHITECTURE/PROCESS.

3.                        Abstraction.

4.                        Verbal documents using the formal definitions in (1) for:

                            ·                Design document

                            ·                Test design document.

 

3.3.3 Practical Exercising

Perform the design stage.

3.4 Detailed Design

3.4.1 Lecture

1.                        Decompose processes into PROCEDUREs and FUNCTIONs.

2.                        Synthesis semantics of procedures and functions.

3.                        Local variables inside a process:

3.1                   Static variables.

3.2                   Automatic variables.

3.3                   Semantics of variables in the synthesis process.

4.                        Coding styles for: synthesis and tests.

3.4.2 Workshop

The detailed design documents will be derived by formal definition using VHDL tools. Related issues:

                            ·          For each process, perform structured procedural decomposition.

                            ·          Global variables.

                            ·          Private information inside an ARCHITECTURE/PROCESS.

 

The same techniques are applicable also to test programs.

3.4.3 Practical Exercising

Perform the detailed design stage.

3.5 Information Organization

3.5.1 Lecture

                            ·          Hierarchical organization using libraries.

                            ·          Naming convention.

                            ·          Configuration management processes.

3.5.2 Workshop

Analyze a design which does not follow information organization techniques.

 

3.5.3 Practical Exercising

Organize the design.

3.6 Testing

3.6.1 Lecture

                            ·          Testing techniques.

                            ·          Positive versus negative tests.

3.6.2 Workshop

TBD

3.6.3 Practical Exercising

TBD

 

 

4. Hours Allocation

Subject

Lecture

Workshop

Exercising

 in class

Total Hours

HW Design flow

4

4

4

12

System Specification

4

4

8

16

Design

8

8

4

20

Detailed Design

8

8

4

20

Information Organization

4

4

4

12

Testing

4

4

4

12

Total

32

32

28

92