Advanced
Verilog Course Syllabus
1. Course
Objectives
After completing the course the student will:
Be able to design in Verilog towards effective synthesis results.
Be able to find differences between High-Level and Low-Level simulation results.
Understand the semantics of synthesis attributes and directives.
Program an FPGA while injecting real signals.
2. General Description
The course is composed of:
The theory.
Workshops in which the process of analyzing given designs and understanding their semantics, is performed.
Practical exercising using Verilog tools.
This document describes:
The subjects and the exercises to be given in the course.
Allocation of hours.
3. Course Subjects
3.1 Behavioral description
towards Synthesis
3.1.1 Lecture
Review of Sequential and Concurrent statements.
Sequential Statements:
Assignment statements
Conditional statements.
Loop
statements.
Synthesis semantics of conditional and While/Loop statements.
Races and hazards.
3.1.2 Workshop
Given 4 high level architectures which find the minimum of two numbers. Only two give the same results after being synthesized. Analyzing these architectures and their performance (timing versus space).
Design an ALU.
Resolving a bit.
Given several high level architectures to resolve the first bit on:
Serial operation.
Parallel operation.
Races and Hazards.
3.1.3 Practical Exercising
Synthesizing and implementation of a design in an FPGA.
Comparing High-Level and Low Level simulation results.
3.2 Synthesis of State Machine
3.2.1 Lecture
1. Combinational networks.
2.
Melay machine.
3. FSM coding styles.
4. State Encoding: Binary, Grey, One-Hot.
5. Synthesis results:
Reports.
Critical path
3.2.1 Workshop
The example is composed of: 1) a µprocessor, 2) its associated peripherals and 3) System Bus Controller (SBC).
The design of the SBC will be presented including the problems in the synthesis process.
UART.
3.2.2 Practical exercising
Write a state machine.
Write and run a test program.
Synthesize, and run the gate-level on the simulator.
Compare the high-level and low -level simulation results.
3.3 Synthesis process
3.3.1 Lecture
Synthesis Attributes
Clock
Timing Constrains.
Hierarchy.
Buses
Translate/Translate-off
Black Box.
Shared resources.
Encoding states and Enumeration type.
3.3.2 Workshop
1. Given several architectures corresponding to the same ENTITY, we have to find the differences in high level design and low level design when using:
Clock.
Timing constraints.
Shared resources.
Encoding states and enumeration type.
The differences will be found by:
Structural analysis of the synthesized design.
Comparing the high-level and low-level simulation results.
2. Adding constraints to a design and checking whether the design meets the constraints.
3.3.3 Practical exercising
Synthesize, and run the gate-level on the simulator using different attributes and directives.
Compare the high-level and low -level simulation results.
Program an FPGA and inject real signals.
3.4 Software engineering with Verilog
3.4.1 Lecture
Managing shared libraries. Testing and verification.
Organizing the design.
4. Hours Allocation
|
Subject |
Lecture |
Workshop |
Exercising in class |
Total Hours |
|
Behavioral description towards Synthesis |
2 |
8 |
4 |
14 |
|
Synthesis of State Machine |
4 |
4 |
4 |
12 |
|
Synthesis process |
4 |
4 |
4 |
12 |
|
ýSoftware engineering with Verilog |
2 |
0 |
0 |
2 |
|
Total |
12 |
16 |
12 |
40 |
5. Bibliography
[Chang97] K.C. Chang, Digital Design and Modeling with VHDL and Synthesis,
IEE Computer Society Press, ISBN 0-816-7716-3.
[Navami] Zainalabedin Navami VHDL Analysis and modeling of Digital Systems.
McGraw-Hill series in electrical and computer engineering, ISBN 0-07-046472-3.
[DoPer90] Douglas L. Perry, VHDL second edition. McGraw-Hill series on
Computer Engineering, ISBN 0-07-049434-7, McGraw-Hill, 1990.
[LRM88] IEEE Standard VHDL Language Reference Manual- std 1076-1987.
[Ams88] James. R Amstrong. Chip level Modeling
with VHDL.
Cliffs, NJ: Prentice Hall, 1988.
[Coh89] David Cohelho.
A First course in VHDL.
1989.
[LipSc89] Roger Lipsett,
Carl Schaefer,
Description and Design.
[Carison91] Steve Carison, Introduction to HDL-Based DESIGN Using VHDL.
Synopsys Inc, 1991.